Complimentary metal oxide semiconductor field effect transistors (CMOS FETs) are prevalent in integrated circuit technology because they generally demand less power than bipolar transistors. Threshold voltage variations of CMOS transistors, however, are beginning to pose impractical limitations on CMOS devices as power supply voltages are reduced. In a 0.2 micron CMOS technology a 0.4 V distribution in threshold voltages might be anticipated. With a one volt power supply, this distribution can cause large variations in the speed of a logic circuit, such as those used in integrated memory circuits. For example, a threshold voltage of 0.6 V is required in a DRAM memory cell access transistor to insure low sub-threshold voltage leakage currents. If a threshold voltage distribution of 0.4 volts is experienced, there will be instances where little or no excess voltage above threshold voltage is available. As such, data transfer from a memory cell via such a transistor will be very slow.
A basic problem with CMOS access transistors results from the fact that CMOS devices do not function well at low voltages and require the use of higher than desirable power supply voltages, currently around two volts in 0.2 micron CMOS technology. Various techniques have been proposed to compensate for this in CMOS technology. For example, some form of transistor forward body bias, or specialized circuits to compensate for threshold voltage variations can be used.
Various types of lateral MOS transistors have been described and utilized in CMOS technology. Lateral bipolar transistors have received renewed interest with the advent of bipolar complementary metal oxide semiconductor (BiCMOS) technologies.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an access device for use in a low voltage memory device which performs fast read access of memory data.